The invention relates to electrostatic discharge protection apparatus and, more particularly, the invention relates to nMOS devices for providing high performance electrostatic discharge protection to integrated circuits.
Integrated circuits are susceptible to damage from electrostatic discharge (ESD). When an ESD pulse or signal is applied to a conductive connection (e.g., a terminal, pin or pad) to an integrated circuit, the ESD pulse or signal may permanently or temporarily damage or otherwise impair the operation of the integrated circuit. To protect against such damage, the terminal, pin or pad of the integrated circuit is coupled to ground through an ESD protection device that shunts the ESD pulse or signal to ground such that the integrated circuit is not harmed by the discharge.
Grounded-gate nMOS transistors have been used for ESD protection for many years. FIG. 1 depicts a gate-coupled nMOS transistor that derives a gate bias voltage from an ESD pulse using a resistor-capacitor (RC) element. The fast transient of an ESD pulse causes a displacement current to flow in the capacitor C and accumulates a bias voltage across the resistor R. The common node of the RC element is connected to the gate of the nMOS structure. In a conventional gate-coupled nMOS transistor under ESD conditions, the device is driven into bipolar operation by avalanche breakdown of the drain p-well junction, followed by a phenomenon known as bipolar snap back that returns the device to steady-state once the ESD pulse has been safely shunted to ground. The gate-coupled nMOS transistor features a relatively low breakdown voltage because of the MOS-current initiated by the temporary gate bias. The gatecoupled nMOS device has proven to be superior to a grounded-gate nMOS transistor especially for multifinger transistor layouts within the integrated circuit where uniform triggering of all fingers is essential for a high ESD performance. However, a potential problem of the gate-coupled nMOS transistor is that the gate bias is not very well defined. Specifically, the gate bias depends on the amplitude and on the rise time (dV/dt) of the applied ESD pulse as the signal is applied across the RC circuit. Depending on the transient gate voltage, the intended uniform triggering of the nMOS device may or may not be established.
Another way of adjusting the trigger voltage of ESD protection elements and of insuring more uniform current flow is to either establish a gate bias and/or a substrate (p-well) bias using a Zener breakdown device in series with a resistor. FIG. 2 depicts a schematic of an ESD protection device that has an nMOS transistor Q with a Zener diode Z coupled from the gate terminal to a pad of the integrated circuit and a resistor R coupled from the gate terminal to ground. The trigger voltage for the ESD protection device is defined by the Zener diode Z breakdown voltage which can be made lower than the drain/p-well junction breakdown trigger mechanism of FIG. 1. The resistor R serves to shunt leakage current through the Zener diode Z to ground, preventing multiplication by the current gain of the parasitic NPN transistor Qxe2x80x2.
Alternatively, a capacitor C (shown in phantom) can be employed in lieu of the Zener diode Z. The capacitor C provides a trigger current in response to the high dV/dt of the ESD pulse. However, the amount of gate bias is limited in both cases by the forward voltage drop of the base-emitter junction of the parasitic NPN transistor Qxe2x80x2.
Therefore, there is a need in the art for a ESD protection device that does not rely on the ESD amplitude and rise time to bias the ESD device elements.
The disadvantage associated with the prior art are overcome by apparatus for providing electrostatic discharge (ESD) protection having an nMOS transistor with bias simultaneously applied to a gate and a p-well of the nMOS transistor. A bias circuit is fabricated using a plurality of the Zener diodes. The double bias allows for a relatively high gate voltage to be applied to the nMOS transistor enabling the nMOS transistor to be biased to optimum conditions for bipolar snapback.